1. Technical Field
The present invention relates to an improved data processing system and, in particular, to a method and apparatus for optimizing performance in a data processing system. Still more particularly, the present invention provides a method and apparatus for enhancing performance of a design process for a microprocessor.
2. Description of Related Art
Microprocessor designs are becoming more complex, and marketing pressures are reducing the amount of time available to bring new, complex chips to market. These types of progressive changes require new methodologies and tools to develop high speed microprocessors.
One manner of gaining significant efficiencies is to employ a two-phase schedule for getting a microprocessor chip into fabrication. During phase A, information relating to the actual transistors and wiring used in the design are processed in its entirety, whereas during phase B, only wire changes from the phase A are processed. Using this methodology, the fabrication process can be started once phase A data has been processed. In the meantime, wire-only changes can still be in progress during phase B so that improvements in the performance of the microprocessor design can continue to be made. However, in order to analyze the current performance (i.e. frequency) of the chip design using current methods, a timing run of the full chip design model is made. Due to the amount of data to be processed for analysis and the number of steps required to produce the data, a timing run with a full chip design model is usually a time-intensive process.
Therefore, it would be particularly advantageous to provide the ability to shorten the design latency for wire-only changes to a chip in order to allow for more numerous wire-only design iterations during the phase B duration.
A method for analyzing a design or a model of a microprocessor chip model is provided. A base chip model is generated, and it is modified with wire-only changes to produce a modified chip model. The modified chip model is compared to the base chip model to discern the wire-only changes to form a delta chip model. A set of values for RC delays and net capacitance based on the delta chip model is produced, and the modified chip model is timed using the set of values for RC delays and net capacitance on the delta chip model and RC delays and net capacitance on the base chip model, where any net that is represented in both models, the delta chip model""s data prevails.